Full Adder (VHDL)

This passage designs a full adder using VHDL program language.

The program are as follows:

  1. implementation code

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:27:49 05/25/2017 
-- Design Name: 
-- Module Name:    fulladder - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fulladder is
    Port ( A : in  STD_LOGIC;
           B : in  STD_LOGIC;
           C_IN : in  STD_LOGIC;
           S : out  STD_LOGIC;
           C_OUT : out  STD_LOGIC);
end fulladder;

architecture Behavioral of fulladder is

begin
S <= ((NOT A) AND (NOT B) AND C_IN) OR ((NOT A) AND B AND (NOT C_IN)) OR (A AND (NOT B) AND (NOT C_IN)) OR (A AND B AND C_IN);
C_OUT <= ((NOT A) AND B AND C_IN) OR (A AND (NOT B) AND C_IN) OR (A AND B AND (NOT C_IN)) OR (A AND B AND C_IN);

end Behavioral;

 

2. simulation code

--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   15:32:53 05/25/2017
-- Design Name:   
-- Module Name:   F:/VHDL/VHDL_LESSON/fulladder/FULLADDER_SIMULATION.vhd
-- Project Name:  fulladder
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: fulladder
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY FULLADDER_SIMULATION IS
END FULLADDER_SIMULATION;
 
ARCHITECTURE behavior OF FULLADDER_SIMULATION IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT fulladder
    PORT(
         A : IN  std_logic;
         B : IN  std_logic;
         C_IN : IN  std_logic;
         S : OUT  std_logic;
         C_OUT : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal A : std_logic := '0';
   signal B : std_logic := '0';
   signal C_IN : std_logic := '0';

 	--Outputs
   signal S : std_logic;
   signal C_OUT : std_logic;
   -- No clocks detected in port list. Replace <clock> below with 
   -- appropriate port name 
 

 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: fulladder PORT MAP (
          A => A,
          B => B,
          C_IN => C_IN,
          S => S,
          C_OUT => C_OUT
        );

   INIT:PROCESS
	BEGIN
	A    <= '0';
	B    <= '0';
	C_IN <= '0';
	WAIT FOR 1 NS;
	
	A    <= '0';
	B    <= '0';
	C_IN <= '1';
	WAIT FOR 1 NS;
	
	A    <= '0';
	B    <= '1';
	C_IN <= '0';
	WAIT FOR 1 NS;
	
	A    <= '0';
	B    <= '1';
	C_IN <= '1';
	WAIT FOR 1 NS;
	
	A    <= '1';
	B    <= '0';
	C_IN <= '0';
	WAIT FOR 1 NS;
	
	A    <= '1';
	B    <= '0';
	C_IN <= '1';
	WAIT FOR 1 NS;
	
	A    <= '1';
	B    <= '1';
	C_IN <= '0';
	WAIT FOR 1 NS;
	
	A    <= '1';
	B    <= '1';
	C_IN <= '1';
	WAIT FOR 1 NS;
	
	END PROCESS;

END;

 

3. simulation result

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8 + 12 =

34 + = 43