4-to-2 data selector (VHDL)

This passage designs a 4-to-2 data selector using VHDL program language.

The program are as follows:

  1. implementation code

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    08:28:02 05/25/2017 
-- Design Name: 
-- Module Name:    choose4_1 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity choose4_1 is
    Port ( a1 : in  STD_LOGIC;
           a2 : in  STD_LOGIC;
           a3 : in  STD_LOGIC;
           a4 : in  STD_LOGIC;
           select_s : in  STD_LOGIC_VECTOR (1 downto 0);
           out_s : out  STD_LOGIC);
end choose4_1;

architecture Behavioral of choose4_1 is

begin
out_s<=a1 when select_s="00" else
   a2 when select_s="01" else
	a3 when select_s="10" else
	a4 ;


end Behavioral;

2. simulation code

--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   14:49:58 05/25/2017
-- Design Name:   
-- Module Name:   F:/VHDL/VHDL_LESSON/choose4_1/choose4_1_simulation.vhd
-- Project Name:  choose4_1
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: choose4_1
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY choose4_1_simulation IS
END choose4_1_simulation;
 
ARCHITECTURE behavior OF choose4_1_simulation IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT choose4_1
    PORT(
         a1 : IN  std_logic;
         a2 : IN  std_logic;
         a3 : IN  std_logic;
         a4 : IN  std_logic;
         select_s : IN  std_logic_vector(1 downto 0);
         out_s : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal a1 : std_logic := '0';
   signal a2 : std_logic := '0';
   signal a3 : std_logic := '0';
   signal a4 : std_logic := '0';
   signal select_s : std_logic_vector(1 downto 0) := (others => '0');

 	--Outputs
   signal out_s : std_logic;
   -- No clocks detected in port list. Replace <clock> below with 
   -- appropriate port name 
 

 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: choose4_1 PORT MAP (
          a1 => a1,
          a2 => a2,
          a3 => a3,
          a4 => a4,
          select_s => select_s,
          out_s => out_s
        );

   INIT:PROCESS
	BEGIN
	a1 <= '0';
	a2 <= '0';
	a3 <= '0';
	a4 <= '0';
	select_s <= "00";
	WAIT FOR 1 NS;
	a1 <= '0';
	a2 <= '0';
	a3 <= '0';
	a4 <= '0';
	select_s <= "01";
	WAIT FOR 1 NS;
	a1 <= '0';
	a2 <= '0';
	a3 <= '0';
	a4 <= '0';
	select_s <= "10";
	WAIT FOR 1 NS;
	a1 <= '0';
	a2 <= '0';
	a3 <= '0';
	a4 <= '0';
	select_s <= "11";
	WAIT FOR 1 NS;
	
	a1 <= '0';
	a2 <= '0';
	a3 <= '0';
	a4 <= '1';
	select_s <= "00";
	WAIT FOR 1 NS;
	a1 <= '0';
	a2 <= '0';
	a3 <= '0';
	a4 <= '1';
	select_s <= "01";
	WAIT FOR 1 NS;
	a1 <= '0';
	a2 <= '0';
	a3 <= '0';
	a4 <= '1';
	select_s <= "10";
	WAIT FOR 1 NS;
	a1 <= '0';
	a2 <= '0';
	a3 <= '0';
	a4 <= '1';
	select_s <= "11";
	WAIT FOR 1 NS;
	
	a1 <= '0';
	a2 <= '0';
	a3 <= '1';
	a4 <= '0';
	select_s <= "00";
	WAIT FOR 1 NS;
	a1 <= '0';
	a2 <= '0';
	a3 <= '1';
	a4 <= '0';
	select_s <= "01";
	WAIT FOR 1 NS;
	a1 <= '0';
	a2 <= '0';
	a3 <= '1';
	a4 <= '0';
	select_s <= "10";
	WAIT FOR 1 NS;
	a1 <= '0';
	a2 <= '0';
	a3 <= '1';
	a4 <= '0';
	select_s <= "11";
	WAIT FOR 1 NS;
	
	a1 <= '0';
	a2 <= '0';
	a3 <= '1';
	a4 <= '1';
	select_s <= "00";
	WAIT FOR 1 NS;
	a1 <= '0';
	a2 <= '0';
	a3 <= '1';
	a4 <= '1';
	select_s <= "01";
	WAIT FOR 1 NS;
	a1 <= '0';
	a2 <= '0';
	a3 <= '1';
	a4 <= '1';
	select_s <= "10";
	WAIT FOR 1 NS;
	a1 <= '0';
	a2 <= '0';
	a3 <= '1';
	a4 <= '1';
	select_s <= "11";
	WAIT FOR 1 NS;
	
	a1 <= '0';
	a2 <= '1';
	a3 <= '0';
	a4 <= '0';
	select_s <= "00";
	WAIT FOR 1 NS;
	a1 <= '0';
	a2 <= '1';
	a3 <= '0';
	a4 <= '0';
	select_s <= "01";
	WAIT FOR 1 NS;
	a1 <= '0';
	a2 <= '1';
	a3 <= '0';
	a4 <= '0';
	select_s <= "10";
	WAIT FOR 1 NS;
	a1 <= '0';
	a2 <= '1';
	a3 <= '0';
	a4 <= '0';
	select_s <= "11";
	WAIT FOR 1 NS;
	
	a1 <= '0';
	a2 <= '1';
	a3 <= '0';
	a4 <= '1';
	select_s <= "00";
	WAIT FOR 1 NS;
	a1 <= '0';
	a2 <= '1';
	a3 <= '0';
	a4 <= '1';
	select_s <= "01";
	WAIT FOR 1 NS;
	a1 <= '0';
	a2 <= '1';
	a3 <= '0';
	a4 <= '1';
	select_s <= "10";
	WAIT FOR 1 NS;
	a1 <= '0';
	a2 <= '1';
	a3 <= '0';
	a4 <= '1';
	select_s <= "11";
	WAIT FOR 1 NS;
	
	a1 <= '0';
	a2 <= '1';
	a3 <= '1';
	a4 <= '0';
	select_s <= "00";
	WAIT FOR 1 NS;
	a1 <= '0';
	a2 <= '1';
	a3 <= '1';
	a4 <= '0';
	select_s <= "01";
	WAIT FOR 1 NS;
	a1 <= '0';
	a2 <= '1';
	a3 <= '1';
	a4 <= '0';
	select_s <= "10";
	WAIT FOR 1 NS;
	a1 <= '0';
	a2 <= '1';
	a3 <= '1';
	a4 <= '0';
	select_s <= "11";
	WAIT FOR 1 NS;
	
	a1 <= '0';
	a2 <= '1';
	a3 <= '1';
	a4 <= '1';
	select_s <= "00";
	WAIT FOR 1 NS;
	a1 <= '0';
	a2 <= '1';
	a3 <= '1';
	a4 <= '1';
	select_s <= "01";
	WAIT FOR 1 NS;
	a1 <= '0';
	a2 <= '1';
	a3 <= '1';
	a4 <= '1';
	select_s <= "10";
	WAIT FOR 1 NS;
	a1 <= '0';
	a2 <= '1';
	a3 <= '1';
	a4 <= '1';
	select_s <= "11";
	WAIT FOR 1 NS;
	
	a1 <= '1';
	a2 <= '0';
	a3 <= '0';
	a4 <= '0';
	select_s <= "00";
	WAIT FOR 1 NS;
	a1 <= '1';
	a2 <= '0';
	a3 <= '0';
	a4 <= '0';
	select_s <= "01";
	WAIT FOR 1 NS;
	a1 <= '1';
	a2 <= '0';
	a3 <= '0';
	a4 <= '0';
	select_s <= "10";
	WAIT FOR 1 NS;
	a1 <= '1';
	a2 <= '0';
	a3 <= '0';
	a4 <= '0';
	select_s <= "11";
	WAIT FOR 1 NS;
	
	a1 <= '1';
	a2 <= '0';
	a3 <= '0';
	a4 <= '1';
	select_s <= "00";
	WAIT FOR 1 NS;
	a1 <= '1';
	a2 <= '0';
	a3 <= '0';
	a4 <= '1';
	select_s <= "01";
	WAIT FOR 1 NS;
	a1 <= '1';
	a2 <= '0';
	a3 <= '0';
	a4 <= '1';
	select_s <= "10";
	WAIT FOR 1 NS;
	a1 <= '1';
	a2 <= '0';
	a3 <= '0';
	a4 <= '1';
	select_s <= "11";
	WAIT FOR 1 NS;
	
	a1 <= '1';
	a2 <= '0';
	a3 <= '1';
	a4 <= '0';
	select_s <= "00";
	WAIT FOR 1 NS;
	a1 <= '1';
	a2 <= '0';
	a3 <= '1';
	a4 <= '0';
	select_s <= "01";
	WAIT FOR 1 NS;
	a1 <= '1';
	a2 <= '0';
	a3 <= '1';
	a4 <= '0';
	select_s <= "10";
	WAIT FOR 1 NS;
	a1 <= '1';
	a2 <= '0';
	a3 <= '1';
	a4 <= '0';
	select_s <= "11";
	WAIT FOR 1 NS;
	
	a1 <= '1';
	a2 <= '0';
	a3 <= '1';
	a4 <= '1';
	select_s <= "00";
	WAIT FOR 1 NS;
	a1 <= '1';
	a2 <= '0';
	a3 <= '1';
	a4 <= '1';
	select_s <= "01";
	WAIT FOR 1 NS;
	a1 <= '1';
	a2 <= '0';
	a3 <= '1';
	a4 <= '1';
	select_s <= "10";
	WAIT FOR 1 NS;
	a1 <= '1';
	a2 <= '0';
	a3 <= '1';
	a4 <= '1';
	select_s <= "11";
	WAIT FOR 1 NS;
	
	a1 <= '1';
	a2 <= '1';
	a3 <= '0';
	a4 <= '0';
	select_s <= "00";
	WAIT FOR 1 NS;
	a1 <= '1';
	a2 <= '1';
	a3 <= '0';
	a4 <= '0';
	select_s <= "01";
	WAIT FOR 1 NS;
	a1 <= '1';
	a2 <= '1';
	a3 <= '0';
	a4 <= '0';
	select_s <= "10";
	WAIT FOR 1 NS;
	a1 <= '1';
	a2 <= '1';
	a3 <= '0';
	a4 <= '0';
	select_s <= "11";
	WAIT FOR 1 NS;
	
	a1 <= '1';
	a2 <= '1';
	a3 <= '0';
	a4 <= '1';
	select_s <= "00";
	WAIT FOR 1 NS;
	a1 <= '1';
	a2 <= '1';
	a3 <= '0';
	a4 <= '1';
	select_s <= "01";
	WAIT FOR 1 NS;
	a1 <= '1';
	a2 <= '1';
	a3 <= '0';
	a4 <= '1';
	select_s <= "10";
	WAIT FOR 1 NS;
	a1 <= '1';
	a2 <= '1';
	a3 <= '0';
	a4 <= '1';
	select_s <= "11";
	WAIT FOR 1 NS;
	
	a1 <= '1';
	a2 <= '1';
	a3 <= '1';
	a4 <= '0';
	select_s <= "00";
	WAIT FOR 1 NS;
	a1 <= '1';
	a2 <= '1';
	a3 <= '1';
	a4 <= '0';
	select_s <= "01";
	WAIT FOR 1 NS;
	a1 <= '1';
	a2 <= '1';
	a3 <= '1';
	a4 <= '0';
	select_s <= "10";
	WAIT FOR 1 NS;
	a1 <= '1';
	a2 <= '1';
	a3 <= '1';
	a4 <= '0';
	select_s <= "11";
	WAIT FOR 1 NS;
	
	a1 <= '1';
	a2 <= '1';
	a3 <= '1';
	a4 <= '1';
	select_s <= "00";
	WAIT FOR 1 NS;
	a1 <= '1';
	a2 <= '1';
	a3 <= '1';
	a4 <= '1';
	select_s <= "01";
	WAIT FOR 1 NS;
	a1 <= '1';
	a2 <= '1';
	a3 <= '1';
	a4 <= '1';
	select_s <= "10";
	WAIT FOR 1 NS;
	a1 <= '1';
	a2 <= '1';
	a3 <= '1';
	a4 <= '1';
	select_s <= "11";
	WAIT FOR 1 NS;
	
	
	END PROCESS;

END;

3. simulation result

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