3-8 decoder (VHDL)

This passage designs a 3-8 decoder using VHDL program language.

The program are as follows:

  1. implementation code

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:08:08 05/25/2017 
-- Design Name: 
-- Module Name:    decoder38 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity decoder38 is
    Port ( in_s : in  STD_LOGIC_VECTOR (2 downto 0);
           out_s : out  STD_LOGIC_VECTOR (7 downto 0));
end decoder38;

architecture Behavioral of decoder38 is

begin
out_s<="11111110" WHEN in_s="000" ELSE
       "11111101" WHEN in_s="001" ELSE
		 "11111011" WHEN in_s="010" ELSE
		 "11110111" WHEN in_s="011" ELSE
		 "11101111" WHEN in_s="100" ELSE
		 "11011111" WHEN in_s="101" ELSE
		 "10111111" WHEN in_s="110" ELSE
		 "01111111";


end Behavioral;

2. simulation code

--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   15:09:44 05/25/2017
-- Design Name:   
-- Module Name:   F:/VHDL/VHDL_LESSON/decoder38/decoder38_simulation.vhd
-- Project Name:  decoder38
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: decoder38
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY decoder38_simulation IS
END decoder38_simulation;
 
ARCHITECTURE behavior OF decoder38_simulation IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT decoder38
    PORT(
         in_s : IN  std_logic_vector(2 downto 0);
         out_s : OUT  std_logic_vector(7 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal in_s : std_logic_vector(2 downto 0) := (others => '0');

 	--Outputs
   signal out_s : std_logic_vector(7 downto 0);
   -- No clocks detected in port list. Replace <clock> below with 
   -- appropriate port name 
 

 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: decoder38 PORT MAP (
          in_s => in_s,
          out_s => out_s
        );

   INIT:PROCESS
	BEGIN
	in_s<="000";
	WAIT FOR 1 NS;
	
	in_s<="001";
	WAIT FOR 1 NS;
	
	in_s<="010";
	WAIT FOR 1 NS;
	
	in_s<="011";
	WAIT FOR 1 NS;
	
	in_s<="100";
	WAIT FOR 1 NS;
	
	in_s<="101";
	WAIT FOR 1 NS;
	
	in_s<="110";
	WAIT FOR 1 NS;
	
	in_s<="111";
	WAIT FOR 1 NS;
	
	END PROCESS;

END;

3. simulation result

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4 × 4 =

3 + = 13