在Code Composer Studio(CCS) 5.3中设置target configuration的步骤

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在本文中将详细介绍如何在Code Composer Studio (CCS)中设置下载用的target configuration和仿真用的target configuration。

环境:

开发板:TMDSEVM6670LE

模拟器:XDS560v2 Emulator

电源: 自带电源

下载用的target configuration

步骤:

  • Step 1:在CCS 5.3中将界面切换到CCS Debug,这个按钮在软件界面的右上角。如果没有,请点击”CCS Edit”左边的添加按钮,将CCS Debug加上去。按钮如下图所示。

1

  • Step 2:点击当前界面左下角的按钮,如下图所示。2弹出的界面如下图所示3
  • Step 3:在该界面单击右键,并选择New Target Configuration,如下图所示。4
  • Step 4:输入名字,还可以设置文件的存放位置(在本文中没有修改存放位置),最后单击Finish。如下图所示。5
  • Step 5:在Connection中选择Blackhawk XDS560v2-USB System Trace Emulator,在Board or Device后面输入过滤文字C6670(因为我的开发板上的DSP芯片是C6670),之后在下面TMS320C6670前面的复选框上打上√,单击Save和Test Connection。(注意:在单击Test Connection之前要把开发板用USB连接到电脑上并给开发板供电。)6
    如果能够连接成功,会出现以下信息。

    [Start]
    
    Execute the command:
    
    %ccs_base%/common/uscif/dbgjtag.exe -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity
    
    [Result]
    
    
    -----[Print the board config pathname(s)]------------------------------------
    
    C:\Users\chengkai\AppData\Local\.TI\693494126\
        0\0\BrdDat\testBoard.dat
    
    -----[Print the reset-command software log-file]-----------------------------
    
    This utility has selected a 560/2xx-class product.
    This utility will load the program 'bh560v2u.out'.
    Loaded FPGA Image: C:\ti\ccsv5\ccs_base\common\uscif\dtc_top.jbc
    The library build date was 'Oct  3 2012'.
    The library build time was '22:14:17'.
    The library package version is '5.0.872.0'.
    The library component version is '35.34.40.0'.
    The controller does not use a programmable FPGA.
    The controller has a version number of '5' (0x00000005).
    The controller has an insertion length of '0' (0x00000000).
    The cable+pod has a version number of '8' (0x00000008).
    The cable+pod has a capability number of '7423' (0x00001cff).
    This utility will attempt to reset the controller.
    This utility has successfully reset the controller.
    
    -----[Print the reset-command hardware log-file]-----------------------------
    
    The scan-path will be reset by toggling the JTAG TRST signal.
    The controller is the Nano-TBC VHDL.
    The link is a 560-class second-generation-560 cable.
    The software is configured for Nano-TBC VHDL features.
    The controller will be software reset via its registers.
    The controller has a logic ONE on its EMU[0] input pin.
    The controller has a logic ONE on its EMU[1] input pin.
    The controller will use falling-edge timing on output pins.
    The controller cannot control the timing on input pins.
    The scan-path link-delay has been set to exactly '2' (0x0002).
    The utility logic has not previously detected a power-loss.
    The utility logic is not currently detecting a power-loss.
    Loaded FPGA Image: C:\ti\ccsv5\ccs_base\common\uscif\dtc_top.jbc
    
    -----[The log-file for the JTAG TCLK output generated from the PLL]----------
    
      Test  Size   Coord      MHz    Flag  Result       Description
      ~~~~  ~~~~  ~~~~~~~  ~~~~~~~~  ~~~~  ~~~~~~~~~~~  ~~~~~~~~~~~~~~~~~~~
        1   none  - 01 00  500.0kHz   -    similar      isit internal clock
        2   none  - 01 09  570.3kHz   -    similar      isit internal clock
        3    512  - 01 00  500.0kHz   O    good value   measure path length
        4    128  - 01 00  500.0kHz   O    good value   auto step initial
        5    128  - 01 0D  601.6kHz   O    good value   auto step delta
        6    128  - 01 1C  718.8kHz   O    good value   auto step delta
        7    128  - 01 2E  859.4kHz   O    good value   auto step delta
        8    128  + 00 02  1.031MHz   O    good value   auto step delta
        9    128  + 00 0F  1.234MHz   O    good value   auto step delta
       10    128  + 00 1F  1.484MHz   O    good value   auto step delta
       11    128  + 00 32  1.781MHz   O    good value   auto step delta
       12    128  + 01 04  2.125MHz   O    good value   auto step delta
       13    128  + 01 11  2.531MHz   O    good value   auto step delta
       14    128  + 01 21  3.031MHz   O    good value   auto step delta
       15    128  + 01 34  3.625MHz   O    good value   auto step delta
       16    128  + 02 05  4.313MHz   O    good value   auto step delta
       17    128  + 02 13  5.188MHz   O    good value   auto step delta
       18    128  + 02 23  6.188MHz   O    good value   auto step delta
       19    128  + 02 37  7.438MHz   O    good value   auto step delta
       20    128  + 03 07  8.875MHz   O    good value   auto step delta
       21    128  + 03 15  10.63MHz   O    good value   auto step delta
       22    128  + 03 1E  11.75MHz  {O}   good value   auto step delta
       23    512  + 02 3E  7.875MHz   O    good value   auto power initial
       24    512  + 03 0E  9.750MHz   O    good value   auto power delta
       25    512  + 03 16  10.75MHz   O    good value   auto power delta
       26    512  + 03 1A  11.25MHz   O    good value   auto power delta
       27    512  + 03 1C  11.50MHz   O    good value   auto power delta
       28    512  + 03 1D  11.63MHz   O    good value   auto power delta
       29    512  + 03 1D  11.63MHz   O    good value   auto power delta
       30    512  + 03 13  10.38MHz  {O}   good value   auto margin initial
    
    The first internal/external clock test resuts are:
    The expect frequency was 500000Hz.
    The actual frequency was 499872Hz.
    The delta frequency was 128Hz.
    
    The second internal/external clock test resuts are:
    The expect frequency was 570312Hz.
    The actual frequency was 569214Hz.
    The delta frequency was 1098Hz.
    
    In the scan-path tests:
    The test length was 16384 bits.
    The JTAG IR length was 6 bits.
    The JTAG DR length was 1 bits.
    
    The IR/DR scan-path tests used 30 frequencies.
    The IR/DR scan-path tests used 500.0kHz as the initial frequency.
    The IR/DR scan-path tests used 11.75MHz as the highest frequency.
    The IR/DR scan-path tests used 10.38MHz as the final frequency.
    
    -----[Measure the source and frequency of the final JTAG TCLKR input]--------
    
    The frequency of the JTAG TCLKR input is measured as 10.37MHz.
    
    The frequency of the JTAG TCLKR input and TCLKO output signals are similar.
    The target system likely uses the TCLKO output from the emulator PLL.
    
    -----[Perform the standard path-length test on the JTAG IR and DR]-----------
    
    This path-length test uses blocks of 512 32-bit words.
    
    The test for the JTAG IR instruction path-length succeeded.
    The JTAG IR instruction path-length is 6 bits.
    
    The test for the JTAG DR bypass path-length succeeded.
    The JTAG DR bypass path-length is 1 bits.
    
    -----[Perform the Integrity scan-test on the JTAG IR]------------------------
    
    This test will use blocks of 512 32-bit words.
    This test will be applied just once.
    
    Do a test using 0xFFFFFFFF.
    Scan tests: 1, skipped: 0, failed: 0
    Do a test using 0x00000000.
    Scan tests: 2, skipped: 0, failed: 0
    Do a test using 0xFE03E0E2.
    Scan tests: 3, skipped: 0, failed: 0
    Do a test using 0x01FC1F1D.
    Scan tests: 4, skipped: 0, failed: 0
    Do a test using 0x5533CCAA.
    Scan tests: 5, skipped: 0, failed: 0
    Do a test using 0xAACC3355.
    Scan tests: 6, skipped: 0, failed: 0
    All of the values were scanned correctly.
    
    The JTAG IR Integrity scan-test has succeeded.
    
    -----[Perform the Integrity scan-test on the JTAG DR]------------------------
    
    This test will use blocks of 512 32-bit words.
    This test will be applied just once.
    
    Do a test using 0xFFFFFFFF.
    Scan tests: 1, skipped: 0, failed: 0
    Do a test using 0x00000000.
    Scan tests: 2, skipped: 0, failed: 0
    Do a test using 0xFE03E0E2.
    Scan tests: 3, skipped: 0, failed: 0
    Do a test using 0x01FC1F1D.
    Scan tests: 4, skipped: 0, failed: 0
    Do a test using 0x5533CCAA.
    Scan tests: 5, skipped: 0, failed: 0
    Do a test using 0xAACC3355.
    Scan tests: 6, skipped: 0, failed: 0
    All of the values were scanned correctly.
    
    The JTAG DR Integrity scan-test has succeeded.
    
    [End]

     

  • Step 6:依次选择Advanced -> C66xx_0(此处是选择一个核,选其他的也可以) -> Browse -> Save -> Test Connection。注意:在单击Browse时会弹出一个选择文件的对话框,我们要选择的文件路径为:
    C:\ti\ccsv5\ccs_base\emulation\boards\evmc6670l\gel

    这个路径根据自己安装CCS的路径而定。8

     

    如果测试通过,会出现下面的信息。

    [Start]
    
    Execute the command:
    
    %ccs_base%/common/uscif/dbgjtag.exe -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity
    
    [Result]
    
    
    -----[Print the board config pathname(s)]------------------------------------
    
    C:\Users\chengkai\AppData\Local\.TI\693494126\
        0\0\BrdDat\testBoard.dat
    
    -----[Print the reset-command software log-file]-----------------------------
    
    This utility has selected a 560/2xx-class product.
    This utility will load the program 'bh560v2u.out'.
    Loaded FPGA Image: C:\ti\ccsv5\ccs_base\common\uscif\dtc_top.jbc
    The library build date was 'Oct  3 2012'.
    The library build time was '22:14:17'.
    The library package version is '5.0.872.0'.
    The library component version is '35.34.40.0'.
    The controller does not use a programmable FPGA.
    The controller has a version number of '5' (0x00000005).
    The controller has an insertion length of '0' (0x00000000).
    The cable+pod has a version number of '8' (0x00000008).
    The cable+pod has a capability number of '7423' (0x00001cff).
    This utility will attempt to reset the controller.
    This utility has successfully reset the controller.
    
    -----[Print the reset-command hardware log-file]-----------------------------
    
    The scan-path will be reset by toggling the JTAG TRST signal.
    The controller is the Nano-TBC VHDL.
    The link is a 560-class second-generation-560 cable.
    The software is configured for Nano-TBC VHDL features.
    The controller will be software reset via its registers.
    The controller has a logic ONE on its EMU[0] input pin.
    The controller has a logic ONE on its EMU[1] input pin.
    The controller will use falling-edge timing on output pins.
    The controller cannot control the timing on input pins.
    The scan-path link-delay has been set to exactly '2' (0x0002).
    The utility logic has not previously detected a power-loss.
    The utility logic is not currently detecting a power-loss.
    Loaded FPGA Image: C:\ti\ccsv5\ccs_base\common\uscif\dtc_top.jbc
    
    -----[The log-file for the JTAG TCLK output generated from the PLL]----------
    
      Test  Size   Coord      MHz    Flag  Result       Description
      ~~~~  ~~~~  ~~~~~~~  ~~~~~~~~  ~~~~  ~~~~~~~~~~~  ~~~~~~~~~~~~~~~~~~~
        1   none  - 01 00  500.0kHz   -    similar      isit internal clock
        2   none  - 01 09  570.3kHz   -    similar      isit internal clock
        3    512  - 01 00  500.0kHz   O    good value   measure path length
        4    128  - 01 00  500.0kHz   O    good value   auto step initial
        5    128  - 01 0D  601.6kHz   O    good value   auto step delta
        6    128  - 01 1C  718.8kHz   O    good value   auto step delta
        7    128  - 01 2E  859.4kHz   O    good value   auto step delta
        8    128  + 00 02  1.031MHz   O    good value   auto step delta
        9    128  + 00 0F  1.234MHz   O    good value   auto step delta
       10    128  + 00 1F  1.484MHz   O    good value   auto step delta
       11    128  + 00 32  1.781MHz   O    good value   auto step delta
       12    128  + 01 04  2.125MHz   O    good value   auto step delta
       13    128  + 01 11  2.531MHz   O    good value   auto step delta
       14    128  + 01 21  3.031MHz   O    good value   auto step delta
       15    128  + 01 34  3.625MHz   O    good value   auto step delta
       16    128  + 02 05  4.313MHz   O    good value   auto step delta
       17    128  + 02 13  5.188MHz   O    good value   auto step delta
       18    128  + 02 23  6.188MHz   O    good value   auto step delta
       19    128  + 02 37  7.438MHz   O    good value   auto step delta
       20    128  + 03 07  8.875MHz   O    good value   auto step delta
       21    128  + 03 15  10.63MHz   O    good value   auto step delta
       22    128  + 03 1E  11.75MHz  {O}   good value   auto step delta
       23    512  + 02 3E  7.875MHz   O    good value   auto power initial
       24    512  + 03 0E  9.750MHz   O    good value   auto power delta
       25    512  + 03 16  10.75MHz   O    good value   auto power delta
       26    512  + 03 1A  11.25MHz   O    good value   auto power delta
       27    512  + 03 1C  11.50MHz   O    good value   auto power delta
       28    512  + 03 1D  11.63MHz   O    good value   auto power delta
       29    512  + 03 1D  11.63MHz   O    good value   auto power delta
       30    512  + 03 13  10.38MHz  {O}   good value   auto margin initial
    
    The first internal/external clock test resuts are:
    The expect frequency was 500000Hz.
    The actual frequency was 499110Hz.
    The delta frequency was 890Hz.
    
    The second internal/external clock test resuts are:
    The expect frequency was 570312Hz.
    The actual frequency was 569214Hz.
    The delta frequency was 1098Hz.
    
    In the scan-path tests:
    The test length was 16384 bits.
    The JTAG IR length was 6 bits.
    The JTAG DR length was 1 bits.
    
    The IR/DR scan-path tests used 30 frequencies.
    The IR/DR scan-path tests used 500.0kHz as the initial frequency.
    The IR/DR scan-path tests used 11.75MHz as the highest frequency.
    The IR/DR scan-path tests used 10.38MHz as the final frequency.
    
    -----[Measure the source and frequency of the final JTAG TCLKR input]--------
    
    The frequency of the JTAG TCLKR input is measured as 10.37MHz.
    
    The frequency of the JTAG TCLKR input and TCLKO output signals are similar.
    The target system likely uses the TCLKO output from the emulator PLL.
    
    -----[Perform the standard path-length test on the JTAG IR and DR]-----------
    
    This path-length test uses blocks of 512 32-bit words.
    
    The test for the JTAG IR instruction path-length succeeded.
    The JTAG IR instruction path-length is 6 bits.
    
    The test for the JTAG DR bypass path-length succeeded.
    The JTAG DR bypass path-length is 1 bits.
    
    -----[Perform the Integrity scan-test on the JTAG IR]------------------------
    
    This test will use blocks of 512 32-bit words.
    This test will be applied just once.
    
    Do a test using 0xFFFFFFFF.
    Scan tests: 1, skipped: 0, failed: 0
    Do a test using 0x00000000.
    Scan tests: 2, skipped: 0, failed: 0
    Do a test using 0xFE03E0E2.
    Scan tests: 3, skipped: 0, failed: 0
    Do a test using 0x01FC1F1D.
    Scan tests: 4, skipped: 0, failed: 0
    Do a test using 0x5533CCAA.
    Scan tests: 5, skipped: 0, failed: 0
    Do a test using 0xAACC3355.
    Scan tests: 6, skipped: 0, failed: 0
    All of the values were scanned correctly.
    
    The JTAG IR Integrity scan-test has succeeded.
    
    -----[Perform the Integrity scan-test on the JTAG DR]------------------------
    
    This test will use blocks of 512 32-bit words.
    This test will be applied just once.
    
    Do a test using 0xFFFFFFFF.
    Scan tests: 1, skipped: 0, failed: 0
    Do a test using 0x00000000.
    Scan tests: 2, skipped: 0, failed: 0
    Do a test using 0xFE03E0E2.
    Scan tests: 3, skipped: 0, failed: 0
    Do a test using 0x01FC1F1D.
    Scan tests: 4, skipped: 0, failed: 0
    Do a test using 0x5533CCAA.
    Scan tests: 5, skipped: 0, failed: 0
    Do a test using 0xAACC3355.
    Scan tests: 6, skipped: 0, failed: 0
    All of the values were scanned correctly.
    
    The JTAG DR Integrity scan-test has succeeded.
    
    [End]

     

    这样我们就创建好了Target Configuration。

仿真用的target configuration

步骤:

  • Step 1:在CCS 5.3中将界面切换到CCS Debug,这个按钮在软件界面的右上角。如果没有,请点击”CCS Edit”左边的添加按钮,将CCS Debug加上去。按钮如下图所示。
  • 1
  • Step 2:点击当前界面左下角的按钮,如下图所示。2弹出的界面如下图所示3
  • Step 3:在该界面单击右键,并选择New Target Configuration,如下图所示。4
  • Step 4:输入名字,还可以设置文件的存放位置(在本文中没有修改存放位置),最后单击Finish。如下图所示。
  • Step5:Connection选择Texas Instruments Simulator,Board or Device选择C6670 Device Functional Simulator, Little Endian,最后点击Save。从图中可以发现,有Big Endian和Little Endian,我们使用的是Little Endian。有关这两者的区别请看文末。

 

Big Endian和Little Endian(大小端)

大小端的区别主要是高低位的问题。下面用图来解释。

大端情况

观察上面两个图,在8bit十六进制显示时,0地址是0xAB,1地址是0xCD,换成16bit十六进制显示时,0地址和1地址一起显示是0xABCD。现在我们再来看小端情况

同样的两个数据,8bit十六进制显示的时候是一样的,但是换成16bit十六进制显示时,0地址和1地址一起显示的居然是0xCDAB。这个高低位的显示区别就是大小端的区别。

总结如下:

大端是高地址放在低位,低地址放在高位;

小端是高地址放在高位,低地址放在低位。

其中:0xABCD,AB是高位,CD是低位;在内存中地址是依次递增的,而且每8个bit就是一个地址,从上面的图中就可以看到。